Then the scaling behavior of InAlN/GaN HEMTs on Si is predicted using the extracted extrinsic and intrinsic parameters of devices with different gate lengths ( L g). The device extrinsic and intrinsic parameters are extracted using equivalent circuit model, which is verified by the good agreement between simulated and measured S-parameter values. In this paper, a high-performance 50-nm-gate-length InAlN/GaN HEMT on Si with a high on/off current ( I on/ I off) ratio of 7.28 × 10 6, an average subthreshold swing (SS) of 72 mV/dec, a low drain-induced barrier lowing (DIBL) of 88 mV, an off-state three-terminal breakdown voltage ( BV ds) of 36 V, a current/power gain cutoff frequency ( f T/ f max) of 140/215 GHz, and a Johnson’s figure-of-merit (JFOM) of 5.04 THz V is simultaneously demonstrated. Due to the low cost and the scaling capability of Si substrate, InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions.
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